V54C365164VL Datasheet | Mosel Vitelic

w w w . D a t a S h e e t . c o m MOSEL VITELIC V54C365164VD(L) HIGH PERFORMANCE 225/200/166/143 MHz 3.3 VOLT 4M X 16 SYNCHRONOUS DRAM 4 BANKS X 1Mbit X 16 PRELIMINARY 45 System Frequency (f CK) Clock Cycle Time (t CK3) Clock Access Time (t AC3) CAS Latency = 3 Clock Access Time (t AC2) CAS Latency = 2 Clock Access Time (t AC1) CAS Latency = 1 225 MHz 4.5 ns 4.5 ns 4.5 ns 12 ns 5 200 MHz 5 ns 5 ns 5 ns 12 ns 6 166 MHz 6 ns 5.4 ns 5.5 ns 12 ns 7 143 MHz 7 ns 5.4 ns 5.5 ns 12 ns Features s 4 banks x 1Mbit x 16 organization s High speed data transfer rates up to 225 MHz s Full Synchronous Dynamic RAM, with all signals referenced to clock rising edge s Single Pulsed RAS Interface s Data Mask for byte Control s Four Banks controlled by BA0 & BA1 s Programmable CAS Latency: 1, 2, 3 s Programmable Wrap Sequence: Sequential or Interleave s Programmable Burst Length: 1, 2, 4, 8 and full page for Sequential Type 1, 2, 4, 8 for Interleave Type s Multiple Burst Read with Single Write Operation s Automatic and Controlled Precharge mand s Random Column Address every CLK (1-N Rule) s Suspend Mode and Power Down Mode s Auto Refresh and Self Refresh s Refresh Interval: 4096 cycles/64 ms s Available in 54 Pin 400 mil TSOP-II s LVTTL Interface s Single +3.3 V ±0.3 V Power Supply Description The V54C365164VD(L) is a four bank Synchronous DRAM organized as 4 banks x 1Mbit x 16. The V54C365164VD(L) achieves high speed data transfer rates up to 225 MHz by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock All of the control, address, data input and output circuits are synchronized with the positive edge of an externally supplied clock. Operating the four memory banks in an interleaved fashion allows random access operation to occur at higher rate than is possible with standard DRAMs. A sequential and gapless data rate of up to 225 MHz is possible depending on burst length, CAS latency and speed...